Apparatus for and method of releasing stuck virtual circuits in an asynchronous transfer mode network

ABSTRACT

An apparatus for and a method of locating and releasing stuck virtual circuits in an ATM network device. Memory resources are freed that would otherwise be lost due to the last cell of a frame not being received on a particular virtual circuit. Two flags: a sticky first_cell flag and a last_cell flag, track the status of the receipt of a frame over a virtual circuit. The software periodically examines the two flags and if both the first_cell flag and last_cell flags are found cleared then a ‘stuck’ virtual circuit is identified indicating that the hardware did not detect a first cell of a frame on this particular virtual circuit since the last time the software cleared this bit to ‘0’. In response to the identification of a stuck virtual circuit, the software releases the memory resources consumed by the incomplete frame.

FIELD OF THE INVENTION

The present invention relates generally to data communications networksand more particularly relates to a method of releasing stuck virtualcircuits in an asynchronous transfer mode network.

BACKGROUND OF THE INVENTION Asynchronous Transfer Mode

Currently, there is a growing trend to make Asynchronous Transfer Mode(ATM) networking technology the base of future global communications.ATM has already been adopted as a standard for broadband communicationsby the International Telecommunications Union (ITU) and by the ATMForum, a networking industry consortium.

ATM originated as a telecommunication concept defined by the ComiteConsulatif International Telegraphique et Telephonique (CCITT), nowknown as the ITU, and the American National Standards Institute (ANSI)for carrying user traffic on any User to Network Interface (UNI) and tofacilitate multimedia networking between high speed devices atmulti-megabit data rates. ATM is a method for transferring networktraffic, including voice, video and data, at high speed. Using thisconnection oriented switched networking technology centered around aswitch, a great number of virtual connections can be supported bymultiple applications through the same physical connection. Theswitching technology enables bandwidth to be dedicated for eachapplication, overcoming the problems that exist in a shared medianetworking technology, like Ethernet, Token Ring and Fiber DistributedData Interface (FDDI). ATM allows different types of physical layertechnology to share the same higher layer—the ATM layer.

ATM is a connection oriented transport service. To access the ATMnetwork, a station requests a virtual circuit between itself and otherend stations, using the signaling protocol to the ATM switch. ATMprovides the User Network Interface (UNI) that is typically used tointerconnect an ATM user with an ATM switch that is managed as part ofthe same network.

The current standard solution for routing in a private ATM network isdescribed in Private Network Node Interface (PNNI) Phase 0 and Phase 1specifications published by the ATM Forum. The previous Phase 0 draftspecification is referred to as Interim Inter-Switch Signaling Protocol(IISP). The goal of the PNNI specifications is to provide customers ofATM network equipment some level of multi-vendor interoperability.

ATM uses very short, fixed length packets called cells. The first fivebytes, called the header, of each cell contain the information necessaryto deliver the cell to its destination. The cell header also providesthe network with the ability to implement congestion control and trafficmanagement mechanisms. The fixed length cells offer smaller and morepredictable switching delays as cell switching is less complex thanvariable length packet switching and can be accomplished in hardware formany cells in parallel. The cell format also allows for multi-protocoltransmissions. Since ATM is protocol transparent, the various protocolscan be transported at the same time. With ATM, phone, fax, video, dataand other information can be transported simultaneously.

A diagram illustrating the format of an ATM cell including the cellheader format across the UNI is shown in FIG. 1. The header comprises an8-bit Virtual Path Indicator (VPI) and a 16-bit Virtual CircuitIndicator (VCI). A four-bit Generic Flow Control (GFC) field supportsmultiplexing functions. The GFC mechanism is intended to support simpleflow control in ATM connections. The Cell Loss Priority (CLP) one-bitfield corresponds to the loss priority of a cell. In operation, lowerpriority cells (i.e. CLP=1) can be discarded under congestionsituations. The Header Error Check (HEC) is an 8-bit field that is usedfor header error detection and correction. The importance of theinformation in the header requires use of the HEC. The payload followsthe HEC field in the ATM cell header and comprises 48 bytes.

The Payload Identifier Type (PTI) is a 3-bit cell header field forencoding information regarding ATM Adaptation Layer (AAL) and ExplicitForward Congestion Indication (EFCI). The AAL is a collection ofstandardized protocols that adapts user traffic to a cell format. AAL5is the protocol standard used to support the transport of Variable BitRate (VBR) traffic and signaling messages. EFCI is a one-bit fieldcontaining information whether congestion at an intermediate node hasbeen experienced. The EFCI bit is set when a threshold has beenexceeded.

ATM Adaptation Layer

In the AAL5 protocol, every AAL frame to be transmitted over the ATMnetwork is segmented into cells. The last cell of the frame is indicatedin the ATM cell header in the PTI field of the cell header. Inparticular, the last cell is indicated by the third bit in the PTI fieldbeing cleared, the second bit a don't care and the first bit being set,i.e. PTI=1 or 3. An ATM network device that receives AAL5 frames mustreassemble all the cells received over each Virtual Circuit (VC), i.e.VPI/VCI pair, until the last cell of the frame is received. After thelast cell of the cell is received, the entire frame is available and canbe sent to its corresponding destination port, i.e. Ethernet port, host,etc.

A problem occurs, however, in the event the last cell of the frame on aspecific VC gets lost and no subsequent ‘last cell’ is received (evenfrom the next frame) on the VC. In the event the last cell is notreceived, the previously received cells of the frame remain stored inthe network device and consume memory resources that are never releasedsince a last cell indication will never be received on the specific VC.The problem is compounded in an ATM network device that establishes alarge number of VCs (i.e. several thousand) wherein the last cell islost for a large percentage of the VCs. In this case, a majority of thememory resources may be consumed and not available for other VCs.

For example, a network device such as an ATM switch or edge device thatis connected to the ATM network may be accidentally disconnected. Allvirtual circuit connections that were already established and that werein the midst of receiving frames, will never be completed and closed.The frames waiting to complete consume memory resources and depending onthe number of incomplete frames, the amount of memory may be large.

Consider an ATM edge device adapted to transport 10 Mbps Ethernet overthe ATM network. Assume each Ethernet frame comprises 1518 bytes, thusoccupying 32 ATM cells to send the corresponding AAL5 frame. Assumingone thousand open connections at the time the device is disconnectedfrom the network, this translates to approximately 1.5 Mbytes of memory.Depending on the size of the memory in the device, this may amount to asizeable portion of the memory. Note that even a relatively smallportion of memory, e.g., 5 or 10%, creates a problem since the memoryconsumption is cumulative if it is not released.

In some cases, the hardware in the device will timeout and cause thesoftware to clear the call, but the memory consumed by the incompleteframe remains. In other cases, both the virtual circuit connectionremains and the memory is not cleared.

It is therefore desirable to have a mechanism adapted to locate virtualcircuits that are stuck due to lost ‘last cells’ and to release these‘stuck’ virtual circuits thus freeing up memory resources that could beused for new virtual circuits.

SUMMARY OF THE INVENTION

The present invention solves the problems associated with the prior artby providing an apparatus for and a method of locating and releasingstuck virtual circuits in an ATM network device. The invention functionsto free memory resources that would otherwise be lost due to the lastcell of a frame not being received on a particular virtual circuit. Thememory savings made possible by the present invention increase as thenumber of virtual circuits increase wherein the last cell of the framewas not received.

Throughout this document the term stuck virtual circuit is meant todenote a virtual circuit wherein the last cell of a frame beingtransmitted over that virtual circuit is never received. This may becaused for any reason such as an ATM network device losing its ATMconnection due to a disconnection, loss of power, mechanical fault, etc.

The invention utilizes two flags: a first_cell flag and a last_cellflag, to track the status of the receipt of a frame over a virtualcircuit. The hardware sets the last_cell bit to ‘1’ for a specificvirtual circuit when a cell with an end of frame indication is receivedon that virtual circuit. The hardware clears the last_cell bit to ‘0’for a specific virtual circuit when a cell is received without an end offrame indication on that virtual circuit. The hardware sets thefirst_cell bit to ‘1’ for a specific virtual circuit when the first cellof a frame is received on that virtual circuit. Otherwise the hardwaredoes not modify the first cell_bit. The first_cell bit operates as a‘sticky’ bit as the hardware can only set the bit and cannot clear it.The bit can only be cleared by software.

The software periodically examines the two flags and if both thefirst_cell flag and last_cell flags are found cleared then a ‘stuck’virtual circuit is identified. This means that the hardware did notdetect a first cell of a frame on this particular virtual circuit sincethe last time the software cleared this bit to ‘0’.

Once a stuck virtual circuit is detected, the software generates asingle cell adapted to have an end of frame indication. The cell isprocessed as if it was received over the ATM network on the problematicvirtual circuit and will cause the frame to be closed on this particularvirtual circuit, thus releasing the memory resources.

Alternatively, the software writes the VPI and VCI to a hardwareregister and in response, the hardware restores the state of the virtualcircuit back to normal operating state. The hardware comprises theappropriate circuitry and logic to emulate the events that would occurif it had received a cell in error having an end of frame indication.

Preferably, the software scans the first_cell and last_cell bits on aperiodic basis. Alternatively, the software may scan on an irregularbasis such when the software performs regular housekeeping tasks.

There is thus provided in accordance with the present invention a methodof releasing a stuck virtual circuit, wherein the last cell of a frametransmitted on the virtual circuit is not received, the methodcomprising the steps of setting a first_cell flag upon reception of thefirst cell of a frame on the virtual circuit, setting a last_cell flagupon reception of a cell on the virtual circuit having an end of frameindication, clearing the last_cell flag upon reception of a cell on thevirtual circuit not having an end of frame indication, examining thefirst_cell flag and the last_cell flag periodically; and if thefirst_cell flag is set, clearing the first_cell flag, and if, after apredetermined period of time, the first_cell flag is cleared and thelast_cell flag is cleared then identifying the virtual circuit as astuck virtual circuit and releasing memory resources currently consumedby the stuck virtual circuit.

There is also provided in accordance with the present invention a methodof releasing a stuck virtual circuit, wherein the last cell of a frametransmitted on the virtual circuit is not received, the methodcomprising the steps of setting a first_cell bit upon reception of thefirst cell of a frame on the virtual circuit, setting a last_cell bitupon reception of a cell on the virtual circuit having an end of frameindication, clearing the last_cell bit upon reception of a cell on thevirtual circuit not having an end of frame indication, examining on aperiodic basis the first_cell bit and the last_cell bit, and if thefirst_cell bit is set, clearing the first_cell bit, identifying thevirtual circuit as a stuck virtual circuit when a first cell has notbeen received since the first_cell bit was cleared and the last_cell bitis cleared and releasing memory resources currently consumed by thestuck virtual circuit.

There is further provided in accordance with the present invention anapparatus for releasing a stuck virtual circuit, wherein the last cellof a frame transmitted on the virtual circuit is not received comprisinga control memory adapted to store, for each virtual circuit, afirst_cell bit and a last_cell bit, a cell processor operative to set afirst_cell bit upon reception of the first cell of a frame on thevirtual circuit, set a last_cell bit upon reception of a cell on thevirtual circuit having an end of frame indication, clear the last_cellbit upon reception of a cell on the virtual circuit not having an end offrame indication, software means operative on the cell processor toexamining the first_cell bit and the last_cell bit periodically, and ifthe first_cell bit is set, clearing the first_cell bit; and if, after apredetermined period of time, the first_cell bit is cleared and thelast_cell bit is cleared then identifying the virtual circuit as a stuckvirtual circuit and means for releasing memory resources currentlyconsumed by the stuck virtual circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, withreference to the accompanying drawings, wherein:

FIG. 1 is a diagram illustrating the format of an ATM cell including thecell header format across the UNI;

FIG. 2 is a diagram illustrating the format of an AAL5 PDU astransported using a plurality of ATM cells;

FIG. 3 is a block diagram illustrating the internal processing flow ofan ATM network device;

FIG. 4 is a flow diagram illustrating the update functions performed bythe hardware in accordance with the present invention; and

FIG. 5 is a flow diagram illustrating the stuck virtual circuit releasemethod performed by the software in accordance with the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION Notation Used Throughout

The following notation is used throughout this document.

Term Definition AAL ATM Adaptation Layer ANSI American NationalStandards Institute ATM Asynchronous Transfer Mode BUS Broadcast andUnknown Server CAM Content Addressable Memory CCITT Comite ConsulatifInternational Telegraphique et Telephonique CLP Cell Loss Priority CRCCyclic Redundancy Code EFCI Explicit Forward Congestion Indication FDDIFiber Distributed Data Interface GFC Generic Flow Control HEC HeaderError Check IISP Interim Inter-Switch Signaling Protocol ITUInternational Telecommunications Union IVC Incoming VPI/VCI table LANLocal Area Network LANE LAN Emulation LEC LAN Emulation Client LECS LANEmulation Configuration Server LES LAN Emulation Server OC OpticalCarrier PDU Protocol Data Unit PNNI Private Network to Network InterfacePTI Payload Identifier Type SMS Selective Multicast Server UDP UserDatagram Protocol UNI User to Network Interface VC Virtual Circuit

Description of the Invention

The present invention solves the problems associated with the prior artby providing an apparatus for and a method of locating and releasingstuck virtual circuits in an ATM network device. The invention functionsto free memory resources that would otherwise be lost due to the lastcell of a frame not being received on a particular virtual circuit. Thememory savings made possible by the present invention increase as thenumber of virtual circuits increase wherein the last cell of the framewas not received.

Throughout this document the term ‘stuck virtual circuit’ or ‘stuck VC’denotes a virtual circuit wherein the last cell of a frame beingtransmitted over that virtual circuit is never received. This may becaused for any reason such as an ATM network device losing its ATMconnection due to a disconnection, loss of power, mechanical fault, etc.

The present invention is useful for locating those virtual circuits thathave frames waiting to complete. In operation, the invention is adaptedto locate the stuck virtual circuits and perform some action in responsethereto. For example, in one embodiment, the stuck connection may bedeleted and/or the software may be notified to trigger a process thatwill perform housekeeping to clean up the memory resources and the listof active connections.

For illustration purposes, the principles of the present invention aredescribed in the context of an example network device such as an ATMswitch or ATM edge device comprising a plurality of ATM ports. Note,however, it is not intended that the invention be limited to the networkdevice described herein. It is appreciated that one skilled in thenetworking arts may apply the present invention to numerous other typesof network devices as well without departing from the spirit and scopeof the invention. Note that throughout this document, references aremade to AAL5 frames, Ethernet frames and ATM cells which are exampleprotocol data units (PDUs) associated with the AAL5 protocol, Ethernetnetwork and ATM network, respectively. It is appreciated that theinvention may be adapted for use in other types of networks thattransmit other types of PDUs, e.g., packets.

A diagram illustrating the format of an AAL5 PDU as transported using aplurality of ATM cells is shown in FIG. 2. The AAL5 Protocol Data Unit(PDU), generally referenced 30, comprises a payload field 32 of 0 to 64Kbytes, padding field 34 of 0 to 47 bytes, a control field 36 of 2bytes, a length field 38 of 2 bytes and a Cyclic Redundancy Code (CRC)field 40 of 4 bytes. The length of the payload portion of the AAL5 frameis required to be a multiple of 48 bytes, i.e. N×48 bytes. The paddingis used to pad the frame when the length of the payload is not an exactmultiple of 48.

The AAL5 protocol is an asynchronous protocol which functions topacketize the data to be transported. It is analogous to the UserDatagram Protocol (UDP) protocol widely used over the Internet in thatthe AAL5 service is an unreliable transport mechanism with no guaranteeof receipt of the packet.

In an ATM network, the AAL5 frame is segmented into a plurality of ATMcell before being transported over the ATM network to the destination.Each of the ATM cells 42, labeled ATM cell #0 through cell #N, has theformat as shown in FIG. 1. In operation, the AAL5 frame is segmentedinto 48 byte chunks and encapsulated in ATM cells 42. The last cell maycomprise 0 to 40 bytes of padding plus the 8 bytes for the control,length and CRC fields.

A block diagram illustrating the internal processing flow of an ATMnetwork device is shown in FIG. 3. The example network device, generallyreferenced 50, may comprise an edge device or switch for use in an ATMnetwork. The device 50 comprises at least one or more ATM ports. Inaddition, the device may provide standard LAN Emulation services, suchas LEC, BUS, LECS, LES, SMS, etc., as defined by ATM Forum LAN Emulationstandards. LAN Emulation permits Ethernet traffic to be transportedacross ATM circuits. For illustration purposes, the Ethernet and ATMports in the network device have been separated into ingress and egressportions.

In particular, one or more ingress ATM signals 52 are received by ATMingress ports 52. The ingress ATM ports 54 are connected to an ATMnetwork and adapted to receive ingress ATM cells. The ATM ports mayoperate at 155 Mbps (OC-3) or 622 Mbps (OC-12), for example. The ingressports forward the received data to the cell processor 56. The processedcells are forwarded to the appropriate destination egress ports 58 foroutput as one or more ATM egress signals 60. The output ATM ports 58 areconnected to the ATM network and adapted to output egress ATM cells.

Forwarding decisions are made by the cell processor 56 that isconfigured dynamically by the software processing block 62. Ingress ATMcells are input and processed by the cell processor which functions togenerate a forwarding decision. In operation, ATM cells are received andforwarded to the appropriate destination on the ATM network.

The control memory 64 is used by the cell processor in making andprocessing a forwarding decision. Received cells are temporarily storedin the cell memory pending the determination of a forwarding decision.

The apparatus and method of the present invention is operative to bothidentify and resolve a stuck VC condition so as to free up memoryresources for use by other connections. The invention utilizes two flagsper virtual circuit to implement a ‘garbage collection’ function. Inparticular, the two flags are used to track certain information abouteach virtual circuit. One of these flags, i.e. memory bits, is termedthe first cell flag and a second flag is termed the last cell flag. Inone example embodiment, these flags (or bits) are stored in an incomingVPI/VCI (IVC) table stored in the control memory 64.

Each virtual circuit stored has an associated entry in the IVC tablecomprising the VPI/VCI pair 66, first_cell flag (or bit) 68 and alast_cell flag (or bit) 70. It is appreciated that the invention is notlimited to storing the first cell and last cell flags in an IVC table.The flags may be stored in any suitable storage location or table.

In accordance with the present invention, the last_cell flag isoperative to indicate that the last cell (i.e. the latest or mostrecent) received on a virtual circuit included an end of frameindication. The first_cell flag is operative to indicate each time afirst cell of a frame is received. The first_cell flag is preferably setby the hardware and cleared by the software.

In order to be able to release a stuck virtual circuit, it must first bedetected. A stuck virtual circuit may be detected by checking that alonger time than reasonable has passed since the first cell of a framewas received on any particular virtual circuit while the most recentcell received on the virtual circuit did not have an end of frameindication. In implementing this, the example embodiment presentedherein utilizes both hardware and software.

The hardware is operative to update the first_cell and last_cell bits(i.e. flags) after each cell is received by the ATM device on a pervirtual circuit basis. The following rules are performed by the hardwarefor each cell received:

1. The hardware sets the last_cell bit to ‘1’ for a specific virtualcircuit when a cell with an end of frame indication is received on thatvirtual circuit. Note that, as described above, the end of frameindication can be determined using the 3-bit PTI field in the ATM cellheader.

2. The hardware clears the last_cell bit to ‘0’ for a specific virtualcircuit when a cell is received without an end of frame indication onthat virtual circuit.

3. The hardware sets the first_cell bit to ‘1’ for a specific virtualcircuit when the first cell of a frame is received on that virtualcircuit. Note that the first_cell bit operates as a ‘sticky’ bit sincethe hardware can only set the bit and cannot clear it.

4. Otherwise the hardware does not modify the first_cell bit.

Note that the first_cell is adapted to be set by the hardware andcleared by the software. Preferably, the hardware does not have theability to clear the first_cell bit.

The above described rules performed by the hardware are also presentedin the form of a flow diagram in FIG. 4. The cell received for aspecific virtual circuit is first checked for an end of frame indication(step 80). If the cell includes an end of frame indication, thelast_cell bit associated with the specific virtual circuit is set (step88). If the cell is received without an end of frame indication (step82), the last_cell bit associated with the specific virtual circuit iscleared (step 90).

The cell is then checked if it is a first cell. Note that preferably,the checks on first cell and last cell are performed in parallel. If thefirst cell of a frame is received (step 84), the first_cell bitassociated with the specific virtual circuit is set (step 92).Otherwise, the first_cell bit is not modified (step 86).

The software is operative to perform the following processes. At time ofreset, the software initializes the first_cell and last_cell hardwarebits associated with each virtual circuit. The first_cell is initializedto ‘0’ and the last_cell is initialized to ‘1’.

During run time, the software is operative to maintain a list of all theactive virtual circuits within the device. It is adapted to scan all theactive virtual circuits on the list on a periodic basis. Note that thetime between scans may be on the order of a second or more so as toreduce the amount of required computing resources. The software tasks ofthe present invention may be performed in the background while othertasks are in the idle state.

Note also that the invention including the first_cell and last_cell bitmechanism is particularly suited for use with the transport of Ethernetframes. The maximum length of an Ethernet frame is 1518 bytes of data.Considering a line rate of 10 Mbps, this translates to a frame time ofapproximately 10 ms.

Thus, when using the invention in an Ethernet environment, a reasonabletime between the detection of the first cell of consecutive frames is atleast 10 ms. Practically, however, the software process implemented inthe network device does not need to perform the method of the inventionat such speeds. Depending on the software tasks, the time period betweenexecution of the software routine implementing the method of theinvention may be much longer, e.g., one second or longer.

For every virtual circuit scanned, the software is operative to read thetwo bits (i.e. last_cell and first_cell) updated by the hardware asdescribed hereinabove. The software processes the two bits read inaccordance with the following.

first cell=‘1’ (last cell=don't care):

This case signifies that there is no stuck virtual circuit. If thefirst_cell bit is set to a ‘1’ it means that the hardware detected afirst cell of a frame on this particular virtual circuit since the lasttime the software cleared this bit to ‘0’. The value of the last_cellbit is a don't care in this case. The software is operative to reset thefirst_cell bit to ‘0’.

first cell=‘0’ AND last cell=‘1’:

This case also signifies that there is no stuck virtual circuit. If thefirst_cell bit is ‘0’ AND the last_cell bit is set to a ‘1’, it meansthat the hardware did not detect a first cell of a frame on thisparticular virtual circuit since the last time the software cleared thisbit to ‘0’. The last_cell bit set to ‘1’ indicates the end of frame andtherefore this state of the virtual circuit is OK since the entire framewas received. The software does not take any action in this case.

first cell=‘0’ AND last cell=‘0’:

This case signifies that the virtual circuit is stuck. If the first_cellbit is ‘0’ and the last_cell bit is ‘0’, it means that the hardware didnot detect a first cell of a frame on this particular virtual circuitsince the last time the software cleared this bit to ‘0’. The last_cellbit set to ‘0’ indicates that a ‘stuck’ virtual circuit was detectedbecause the end of frame was not received (i.e. the virtual circuit wasnot closed) for a period exceeding a predetermined threshold, e.g., 100ms. If the software performs a scan of the active list of virtualcircuits once every second or longer, than this threshold will have beenexceeded. The software takes action in this case to release the ‘stuck’virtual circuit.

Once a stuck virtual circuit is detected, the software may be adapted toperform any suitable action to release it. Two examples of handling thestuck virtual circuit are described hereinbelow. It is appreciated thatone skilled in the networking arts may implement other mechanisms ofreleasing the stuck virtual circuit without departing from the spiritand scope of the present invention.

A first method of releasing the stuck virtual circuit comprises thesoftware generating a single cell upon detecting a stuck virtualcircuit. The single cell is generated so as to comprise an end of frameindication. The cell is processed as if it was received over the ATMnetwork on the problematic virtual circuit.

In particular, the AAL5 CRC field in the cell should be set so that theframe causes an error. The cell will cause the frame to be closed onthis particular virtual circuit and, since the frame is an error frame,the frame will be discarded. Consequently, all the memory resourcesoccupied (i.e. consumed) by the frame will be released.

Note that the cell generated is made to cause an error on the frame inorder that the frame data previously received and stored in memory willnot be used. Since the last cell was lost, it is desirable to discardthe frame data already received.

A second method of releasing the stuck virtual circuit comprises thesoftware writing to a hardware register dedicated for the purpose ofreleasing the stuck virtual circuit. The software is adapted to writethe VPI and VCI identifying the stuck virtual circuit to this dedicatedregister. In response, the hardware restores the state of the virtualcircuit back to normal operating state. The hardware comprises theappropriate circuitry and logic to emulate the events that would occurif it had received a cell having an end of frame indication and anerroneous AAL5 CRC check. This causes the hardware to restore thevirtual circuit to the normal state and consequently to release all thememory resources previously consumed by the frame.

Note that the above assumes that the device is adapted to comprisehardware that is operative to cleat the memory resources when the lastcell for a frame transmitted over a virtual circuit arrives at thenetwork device.

The above described stuck virtual circuit release method performed bythe software is also presented in the form of a flow diagram in FIG. 5.Initially, after reset, the software creates and maintains a list of allactive virtual circuits (step 100). Upon reset, the software clears thefirst_cell bit and sets the last_cell bit to one (step 102). Then, on aperiodic basis such as during the time the processor is idle, thesoftware scans the active list of virtual circuits including thefirst_cell and last_cell bits (step 104). The bits may be scanned on anirregular basis such as when the processor performs general housekeepingtasks.

If the first_cell equals ‘1’ (step 106), while the last_cell is a don'tcare, then the virtual circuit is declared OK and the first_cell bit iscleared by the software (step 108). If the first_cell is equal to ‘0’and the last_cell is equal to ‘1’ (step 110) then the behavior is deemedto be OK (step 112).

If the first_cell is equal to ‘0’ and the last_cell is equal to ‘0’(step 114) then a stuck virtual circuit has been found (step 116). Asdescribed above, the stuck virtual circuit can be released in anysuitable manner, for example, by generating a signal cell with an end offrame indication or by writing the virtual circuit related information(i.e. VPI and VCI) to a dedicated hardware register that functions torestore the virtual circuit the normal state (step 118).

It is intended that the appended claims cover all such features andadvantages of the invention that fall within the spirit and scope of thepresent invention. As numerous modifications and changes will readilyoccur to those skilled in the art, it is intended that the invention notbe limited to the limited number of embodiments described herein.Accordingly, it will be appreciated that all suitable variations,modifications and equivalents may be resorted to, falling within thespirit and scope of the present invention.

What is claimed is:
 1. A method of releasing a stuck virtual circuit,wherein the last cell of a frame transmitted on said virtual circuit isnot received, said method comprising the steps of: setting a first_cellflag upon reception of the first cell of a frame on said virtualcircuit; setting a last_cell flag upon reception of a cell on saidvirtual circuit having an end of frame indication; clearing saidlast_cell flag upon reception of a cell on said virtual circuit nothaving an end of frame indication; examining said first_cell flag andsaid last_cell flag periodically; and if said first_cell flag is set,clearing said first_cell flag; and if, after a predetermined period oftime, said first_cell flag is cleared and said last_cell flag is clearedthen identifying said virtual circuit as a stuck virtual circuit; andreleasing memory resources currently consumed by said stuck virtualcircuit.
 2. The method according to claim 1, further comprising the stepof generating a single cell with an end of frame indication wherein saidcell is adapted to cause the frame to be received in error such that theframe is subsequently closed and discarded thereby releasing resourcesconsumed by said frame.
 3. The method according to claim 2, wherein saidsingle cell is generated so as to cause a Cyclic Redundancy Code (CRC)check error.
 4. The method according to claim 1, further comprising thestep of providing a means of emulating the action that would normally bytaken upon receiving a cell adapted to cause an error and having an endof frame indication such that said stuck virtual circuit is restored tonormal operating status.
 5. The method according to claim 4, whereinsaid cell is adapted to cause a Cyclic Redundancy Code (CRC) checkerror.
 6. The method according to claim 1, wherein said first_cell flagcomprises a single bit.
 7. The method according to claim 1, wherein saidlast_cell flag comprises a single bit.
 8. The method according to claim1, further comprising the step of maintaining a list of all activevirtual circuits and periodically scanning the first_cell flag and thelast_cell flag associated only with virtual circuits on said activelist.
 9. The method according to claim 1, wherein said predeterminedperiod of time is at least as long as the longest expected frameduration time.
 10. The method according to claim 1, wherein saidpredetermined period of time is greater than or equal to a half second.11. The method according to claim 1, wherein said first_cell flagcomprises a sticky bit whereby said bit is set using hardware means andcleared only using software means.
 12. The method according to claim 1,further comprising the step of identifying said virtual circuit in anormal state when said first_cell flag is set.
 13. The method accordingto claim 1, further comprising the step of identifying said virtualcircuit in a normal state when said first_cell flag is cleared and saidlast_cell flag is set.
 14. A method of releasing a stuck virtualcircuit, wherein the last cell of a frame transmitted on said virtualcircuit is not received, said method comprising the steps of: setting afirst_cell bit upon reception of the first cell of a frame on saidvirtual circuit; setting a last_cell bit upon reception of a cell onsaid virtual circuit having an end of frame indication; clearing saidlast_cell bit upon reception of a cell on said virtual circuit nothaving an end of frame indication; examining on a periodic basis saidfirst_cell bit and said last_cell bit; and if said first_cell bit isset, clearing said first_cell bit; identifying said virtual circuit as astuck virtual circuit when a first cell has not been received since saidfirst_cell bit was cleared and said last_cell bit is cleared; andreleasing memory resources currently consumed by said stuck virtualcircuit.
 15. The method according to claim 14, further comprising thestep of generating a single cell with an end of frame indication whereinsaid cell is adapted to cause the frame to be received in error suchthat the frame is subsequently closed and discarded thereby releasingresources consumed by said frame.
 16. The method according to claim 14,further comprising the step of providing a means of emulating the actionthat would normally by taken upon receiving a cell adapted to cause anerror and having an end of frame indication such that said stuck virtualcircuit is restored to normal operating status.
 17. The method accordingto claim 14, wherein said first_cell bit functions as a sticky bitwhereby said sticky bit is set using hardware means and cleared onlyusing software means.
 18. The method according to claim 14, furthercomprising the step of identifying said virtual circuit in a normalstate when said first_cell bit is set.
 19. The method according to claim14, further comprising the step of identifying said virtual circuit in anormal state when said first_cell bit is cleared and said last_cell bitis set.
 20. An apparatus for releasing a stuck virtual circuit, whereinthe last cell of a frame transmitted on said virtual circuit is notreceived, comprising: a control memory adapted to store, for eachvirtual circuit, a first_cell bit and a last_cell bit; a cell processoroperative to: set a first_cell bit upon reception of the first cell of aframe on said virtual circuit; set a last_cell bit upon reception of acell on said virtual circuit having an end of frame indication; clearsaid last_cell bit upon reception of a cell on said virtual circuit nothaving an end of frame indication; software means operative on said cellprocessor to: examining said first_cell bit and said last_cell bitperiodically; and if said first_cell bit is set, clearing saidfirst_cell bit; and if, after a predetermined period of time, saidfirst_cell bit is cleared and said last_cell bit is cleared thenidentifying said virtual circuit as a stuck virtual circuit; and meansfor releasing memory resources currently consumed by said stuck virtualcircuit.
 21. The apparatus according to claim 20, further comprisingmeans for generating a single cell with an end of frame indicationwherein said cell is adapted to cause the frame to be received in errorsuch that the frame is subsequently closed and discarded therebyreleasing resources consumed by said frame.
 22. The apparatus accordingto claim 20, further comprising means for emulating the action thatwould normally by taken upon receiving a cell adapted to cause an errorand having an end of frame indication such that said stuck virtualcircuit is restored to normal operating status.
 23. The apparatusaccording to claim 20, wherein said first_cell bit functions as a stickybit whereby said sticky bit is set by said cell processor using hardwaremeans and cleared only by said software means.
 24. The apparatusaccording to claim 20, further comprising means for identifying saidvirtual circuit in a normal state when said first_cell bit is set. 25.The apparatus according to claim 20, further comprising means foridentifying said virtual circuit in a normal state when said first_cellbit is cleared and said last_cell bit is set.